1. Technical Field
The present invention relates to a display device, and more particularly, to an array substrate for a display device having a dual-gate structure and preventing an electrical short.
2. Discussion of the Related Art
Recently, as the society has entered an information age, various types of display devices that represent all sorts of electrical signals as visual images have been developed rapidly. For example, a liquid crystal display (LCD) device and an organic light emitting diode (OLED) display device have been widely introduced and used as a substitute for a display device of cathode-ray tube type.
A general LCD device has characteristics of light weight, thinness and low power consumption. A general OLED display device of new flat panel display devices has high brightness and low driving voltage. The OLED display device is a self-emitting type and has excellent characteristics of a view angle, a contrast ratio, a response time and so on.
The LCD device can include array elements on a first substrate and color filters on a second substrate. The array element for the LCD device includes a gate line, a data line, a thin film transistor (TFT) as a switching element and a pixel electrode. The array element for the LCD device may further include a common electrode.
On the other hand, the OLED display device can include array elements on a substrate and an organic light emitting diode connected to each array element. The array element for the OLED display device includes a switching thin film transistor (TFT) (which is connected to a gate line and a data line), a driving TFT (which is connected to the switching TFT), and a power line connected to the driving TFT. The organic light emitting diode includes a first electrode (which is connected to the driving TFT), an organic emitting layer and a second electrode. In the OLED display device, light from the organic emitting layer passes through the first electrode or the second electrode to display an image.
As known, both of the LCD device and the OLED display device according to the related art require the substrate including the array elements. The substrate here may be referred to as an array substrate.
The TFT according to the related art includes a semiconductor layer of amorphous silicon, poly-silicon or an oxide semiconductor material. The TFT including the semiconductor layer of poly-silicon or the oxide semiconductor material has an advantage in mobility such that it is widely used for the OLED display device. Recently, the TFT including the semiconductor layer of the oxide semiconductor material can be made with an improved fabricating process such that it is more widely used. In addition, a dual gate type TFT having improved properties than a single gate type TFT is introduced.
FIG. 1 is a schematic cross-sectional view of an array substrate for the related art OLED display device. A driving region DA and an emitting region EA are defined in each pixel region P among a plurality of pixel regions Ps.
As shown in FIG. 1, the OLED display device according to the related art includes an array substrate 1. For each of a plurality of driving regions DAs in the array substrate 1, a first gate electrode 15 is formed on a substrate 10, and a gate insulating layer 18 is formed on the first gate electrode 15.
In each driving region DA, a semiconductor layer 20, which is formed of an oxide semiconductor material, is formed on the gate insulating layer 18 to correspond to the first gate electrode 15, and an etch stopper 23, which is formed of an inorganic insulating material, is formed on the semiconductor layer 20. The etch stopper 23 includes semiconductor contact holes 25 exposing both ends of the semiconductor layer 20.
A source electrode 33 and a drain electrode 36 are formed on the etch stopper 23. The source and drain electrodes 33 and 36 respectively contact the semiconductor layer 20 through the semiconductor contact holes 25.
A passivation layer 40 including a first drain contact hole 43 is formed on the source and drain electrodes 33 and 36. A portion of the drain electrode 36 is exposed through the first drain contact hole 43. In addition, a gate contact hole “gch” exposing the first gate electrode 15 is formed through the passivation layer 40, the etch stopper 23 and the gate insulating layer 18.
An auxiliary drain electrode 56 contacting the drain electrode 36 through the first drain contact hole 43 is formed on the passivation layer 40. In addition, a second gate electrode 54 contacting the first gate electrode 15 through the gate contact hole “gch” is formed on the passivation layer 40. The second gate electrode 54 is spaced apart from the auxiliary drain electrode 56, overlaps the source electrode 33, and is closely located to the drain electrode 36.
The first gate electrode 15, the semiconductor layer 20, the source electrode 33, the drain electrode 36, the auxiliary drain electrode 56 and the second gate electrode 54 constitute a driving TFT DTr in each driving region DA.
A planarization layer 60 having a flat top surface is formed on the auxiliary drain electrode 56 and the second gate electrode 54. The planarization layer 60 includes a second drain contact hole 63 exposing the auxiliary drain electrode 56.
A first electrode 70 contacting the auxiliary drain electrode 56 through the second drain contact hole 63 is formed on the planarization layer 60. The first electrode 70 is positioned in the emitting region EA. A bank 71 overlapping an edge of the first electrode 70 is formed on the planarization layer 60. The bank 71 is positioned in the driving region DA and surrounds the pixel region P.
An organic emitting layer 73 is formed on the first electrode 70 and in the emitting region EA, and a second electrode 76 is formed on the organic emitting layer 73. The first electrode 70, the organic emitting layer 73 and the second electrode 76 constitute an organic emitting diode E in each emitting region EA.
In FIG. 1, the organic emitting diode E is formed on the substrate 10 with the driving TFT DTr. Alternatively, the organic emitting diode E can be formed on an opposite substrate. In this instance, the array substrate for the OLED display device includes the driving TFT and an electrode as a connection electrode.
On the other hand, the array substrate for the LCD device includes a TFT shown in FIG. 1 and a pixel electrode, which is connected to the TFT, with or without a common electrode. Namely, both the array substrate for the OLED display device and the array substrate for the LCD device include TFTs and electrodes. The TFT in FIG. 1 is a dual gate type TFT.
As illustrated above, in the dual gate type TFT, the first and second gate electrodes 15 and 54 are disposed under and over the semiconductor layer 20, respectively. In addition, the first and second gate electrodes 15 and 54 are in direct contact with each other and are electrically connected to each other.
A channel is securely formed in the semiconductor layer 20 in the dual gate type TFT such that an ON current property of the dual gate type TFT is improved in comparison to a TFT including a single gate electrode. In addition, a stain problem resulting from a non-uniformity of the TFT is decreased such that an image quality is improved.
However, there may be a problem in the operation of the TFT according to the related art. In the related art dual gate type TFT as shown in FIG. 1, an electrical short problem is generated between the drain electrode 36 and the second gate electrode 54 and between the source electrode 33 and the second gate electrode 54. As a result, the TFT is not properly operated.
In more detail, the passivation layer 40, which is formed of an inorganic insulating material, is formed between the drain electrode 36 and the second gate electrode 54 and between the source electrode 33 and the second gate electrode 54, and has a thickness of 2000 to 4000 angstroms. Each of the source and drain electrodes 33 and 36 and the second gate electrode 54 is formed of a low resistance metallic material such as copper (Cu), Cu alloy, aluminum (Al) or Al alloy (AlNd).
Particularly, when the source and drain electrodes 33 and 36 and the second gate electrode 54, each of which is formed of Cu or Al, are exposed to a relatively high temperature, e.g., 200 to 300° C., in a sputtering process or a chemical vapor deposition process, the material of the source and drain electrodes 33 and 36 and the second gate electrode 54 is migrated into the passivation layer 40 such that an electrical short problem is generated between the drain electrode 36 and the second gate electrode 54 and between the source electrode 33 and the second gate electrode 54. FIG. 2 is a picture depicting an example of such Cu migration into the passivation layer 40 causing an electrical short problem. This negatively affects the operation of the dual gate type TFT according to the related art.